Packaging a 40-Gbps Serial Link Using a Wire-Bonded Plastic Ball Grid Array
System-in-Package Design and Test
Advances in cmos technologies let the number of transistors grow much more rapidly than the number of I/Os. This huge discrepancy in growth rates means that the bandwidth of each I/O pin becomes more critical as technology scales down. Processors’ increasing computational capability is driving a need for high-speed links to communicate the processed information.
For the past 10 years, research on these links has focused on improving transceiver circuits to sustain desired data rates.Although this has led to expectations of continued data rate advancements, the nature of link design is changing. Today’s internal circuits can run at tens of gigabits per second (Gbps), but the bandwidth of the channel—the physical medium through which the signal propagates from transmitter output to receiver input—limits link performance.